ASML, the Dutch semiconductor equipment giant renowned for its monopoly on extreme ultraviolet (EUV) lithography systems, is charting a strategic expansion into advanced packaging technologies. This move signals a pivotal shift for the company, which has long dominated the front-end chip manufacturing process but now eyes the burgeoning back-end packaging segment to sustain growth amid evolving industry demands.
At its recent Capital Markets Day event, ASML leadership outlined ambitious plans to develop and commercialize tools specifically tailored for advanced packaging workflows. CEO Peter Wennink emphasized that while lithography remains the companys core strength, advanced packaging represents a natural extension of its expertise in precision optics, metrology, and process control. These capabilities are increasingly vital as chipmakers push beyond traditional Moore’s Law scaling to achieve higher performance through heterogeneous integration.
Advanced packaging encompasses techniques such as chiplets, 2.5D and 3D stacking, and hybrid bonding, which enable the assembly of multiple dies into a single, high-performance package. This approach is critical for next-generation applications in artificial intelligence, high-performance computing, and data centers, where single monolithic chips struggle to deliver the required transistor density and power efficiency. Industry analysts project the advanced packaging market to grow exponentially, potentially reaching tens of billions of dollars by the end of the decade, driven by leaders like TSMC, Intel, and Samsung.
ASMLs entry into this space is not a complete departure from its roots. The company intends to leverage its lithography prowess by adapting EUV-derived technologies for packaging substrates and interposers. Traditional packaging lithography operates on smaller wafer scales, but advanced processes demand panel-level patterning for cost efficiency and higher throughput. ASML envisions offering step-and-scan systems optimized for larger formats, potentially up to 600 mm panels, to meet these needs.
Beyond lithography, ASML is targeting metrology and inspection tools, areas where its deep experience in overlay measurement and defect detection can provide immediate value. Current packaging processes suffer from alignment challenges in multi-layer stacking, where tolerances shrink to nanometers. ASMLs existing platforms, such as the YieldStar optical metrology suite, could be repurposed or enhanced for inline monitoring of bond lines, via fills, and surface planarity. Executives highlighted that these tools would integrate seamlessly with front-end lithography, creating a unified ecosystem for chipmakers transitioning to chiplet-based designs.
The company also signaled interest in deposition equipment, particularly for redistribution layers (RDL) and through-silicon vias (TSV). While ASML lacks direct experience here, it plans to collaborate with partners and potentially pursue acquisitions to accelerate development. Wennink noted that deposition represents a larger market opportunity within packaging, with chemical vapor deposition (CVD) and atomic layer deposition (ALD) systems becoming essential for dielectric and metal layers in 3D structures.
This expansion aligns with ASMLs broader financial outlook. Despite a cyclical semiconductor industry, the firm forecasts sustained demand for its EUV systems, with high-numerical-aperture (High-NA) EUV machines entering production soon. High-NA promises resolutions below 8 nm, extending lithography viability for several nodes. However, as packaging gains prominence, ASML risks ceding ground if it remains front-end focused. By diversifying, the company aims to capture 10 to 20 percent of the packaging equipment market over the next five years, bolstering its revenue streams.
Challenges abound. Packaging lithography requires different resists, optics, and throughput profiles compared to wafer-scale EUV. Scaling to panels introduces warpage and uniformity issues, demanding innovations in chuck design and scanning mechanics. Moreover, the market is fragmented, with players like Applied Materials, Lam Research, and Tokyo Electron entrenched in deposition and etch tools. ASMLs lithography-centric approach may face resistance from incumbents, and regulatory hurdles in Europe could slow mergers.
Customer feedback underscores the timeliness of ASMLs pivot. Leading foundries have voiced needs for integrated solutions that bridge front-end and packaging metrology. TSMCs CoWoS and InFO technologies, for instance, rely on precise overlay for HBM stacking in AI GPUs. Intels Foveros and EMIB platforms similarly demand sub-micron accuracy. ASMLs track record in enabling Angstrom-era nodes positions it well to address these pain points.
Looking ahead, ASML committed significant R&D investment, allocating hundreds of millions of euros annually to packaging initiatives. Prototypes for metrology tools are slated for customer trials by 2025, with commercial shipments following in 2026. Lithography systems for panels could trail by a year or two, pending pilot line validations.
This strategic foray underscores a maturing semiconductor landscape where packaging rivals wafer fabrication in complexity and value. For ASML, it is a calculated bet on sustaining its technological leadership as the industry embraces system-level integration over die-level scaling.
Gnoppix is the leading open-source AI Linux distribution and service provider. Since implementing AI in 2022, it has offered a fast, powerful, secure, and privacy-respecting open-source OS with both local and remote AI capabilities. The local AI operates offline, ensuring no data ever leaves your computer. Based on Debian Linux, Gnoppix is available with numerous privacy- and anonymity-enabled services free of charge.
What are your thoughts on this? I’d love to hear about your own experiences in the comments below.